This invention relates generally to analog-to-digital (A/D) converters and, more particularly, to digital encoding techniques for reducing errors that normally arise during the analog-to-digital conversion process.
One of the most basic devices for converting analog signals into digital form is a parallel analog-to-digital converter. In a parallel A/D converter, an analog input signal is simultaneously compared to a large number of reference levels by a bank of comparators. For n bits of resolution in the digital output of the parallel A/D converter, there are 2.sup.n -1 reference levels and comparators, with each reference level representing a digital increment or step in the digital output. For example, in an eight bit A/D converter, there are 255 reference levels and comparators.
The digital output of the bank of comparators is a series of logical "ones" and a series of logical "zeros," sometimes referred to as thermometer code. The comparators having reference level inputs that are less than or equal to the analog input signal generate outputs of one binary state, such as "ones," and the comparators having reference level inputs that are greater than the analog input signal generate outputs of the other binary state, in this case "zeros." The desired digital output of the A/D converter is the sum of these individual comparator outputs. The preferred approach for generating this sum is not to add the individual comparator outputs but to detect the single one-to-zero transition in the bank of comparators and convert that transition point into some type of binary code.
However, converting the one-to-zero transition point directly into standard binary code may result in large errors in the digital output when two or more transition points are generated by the bank of comparators. These multiple simultaneous transition points, which are usually within a few bit positions of each other, are caused by such factors as fluctuations in the analog input signal during the conversion process and non-matched comparator characteristics.
If two simultaneous transition points are converted into their respective binary codes, the output of the A/D converter will be the logical OR of the two binary codes. For example, suppose that the two simultaneous transition points are one bit position apart. If these two transition points are 0010 and 0011 in standard binary code, representing decimal values of 2 and 3, respectfully, the logical OR of these two codes is 0011. This result is either the correct value or one bit in error. However, if the two transition points are 0111 and 1000 in standard binary code, representing decimal values of 7 and 8, respectively, the logical OR of these two codes is 1111. This result, representing a decimal value of 15, is approximately double the correct value of 7 or 8.
There are several digital encoding techniques that substantially reduce the large errors resulting from the conversion of the one-to-zero transition point directly into standard binary code. These digital encoding techniques rely on the conversion of the one-to-zero transition point into some type of error-reducing intermediate binary code before the conversion into standard binary code. One of these error-reducing codes is the well known Gray code, a unit-distance code in which only one bit is allowed to change between adjacent digital codes.
In the example given above, the decimal values of 2 and 3 are encoded in Gray code as 0011 and 0010, respectively, and the decimal values of 7 and 8 are encoded as 0100 and 1100, respectively. The logical OR of each of these sets of Gray codes is either the correct value or just one bit in error. Because the logical OR of any two adjacent Gray codes is always equal to one of the two digital codes, the error is at most one part in 2.sup.n.
In a typical parallel A/D converter employing Gray code, the one-to-zero transition point is converted into Gray code using a read-only memory. The Gray-encoded output of the read-only memory is then converted into standard binary code by some type of logic circuit, usually a parallel-series arrangement of exclusive-OR gates. However, this type of logic circuit is very slow, requiring n gate delays to convert the Gray-encoded output into standard binary code. A digital encoding technique that has the error-reducing features of Gray code and can be converted into standard binary code in only a single gate delay is a modified Gray code known as quasi-Gray code.
In the example given above, the decimal values of 2 and 3 are encoded in quasi-Gray code as 0011 and 0010, respectively, and the decimal values of 7 and 8 are encoded as 0101 and 1111, respectively. The logical OR of each of these sets of quasi-Gray codes is either the correct value or just one bit in error, providing the same error-reducing performance as Gray code for two transition points separated by one bit position. However, the most commonly used technique for detecting the transition point is a bank of AND gates which cannot generate multiple transition points separated by only one bit position. Therefore, the performance of these digital encoding techniques must be examined for multiple transition points separated by two or more bit positions.
For example, suppose that two simultaneous transition points are two bit positions apart. If these two transition points are 0110 and 0101 in quasi-Gray code, representing decimal values of 5 and 7, respectively, the logical OR of these two codes is 0111, representing a decimal value of 4. This result is either one bit in error or a relatively large three bits in error. The logical OR of these same two decimal values in standard binary code is either the correct value or only two bits in error. Therefore, the error-reducing performance of quasi-Gray is actually worse than standard binary code in this example. Accordingly, there is a need for a digital encoding technique providing improved error performance for simultaneous transition points separated by two or more bit positions. The present invention clearly fulfills this need.